The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a capacitor with a dielectric structure advantageous of reducing leakage current, and a method for fabricating the same.
As dielectric structures of capacitors for sub-60 nm dynamic random access memories (DRAMs), many researchers have attempted to form a thin layer of zirconium oxide (ZrO2) using an atomic layer deposition (ALD) method. However, when an ALD method is used to form a thin layer of ZrO2, ZrO2 is usually crystallized at a low temperature of 300° C. Hence, if a single layer of ZrO2 is used as a dielectric structure, current is likely to leak.
For this reason, a laminate structure including a ZrO layer and an aluminum oxide (Al2O3) layer, which has high crystallization temperature, or an alloy including ZrO2 and Al2O3 is applied to reduce the crystallization.
FIG. 1 illustrates a cross-sectional view of a conventional capacitor structure. The capacitor includes a tower electrode 11, a dielectric structure 12, and an upper electrode 13 formed in sequential order. The dielectric structure 12 includes amorphous thin ZrO2 layer 12A and an amorphous thin Al2O3 layer 12B.
However, since the thin ZrO2 layer and the thin Al2O3 layer are at amorphous phase, relative dielectric constants thereof are usually small. Thus, the thicknesses of the ZrO2 layer and the Al2O3 layer need to be reduced to obtain a desired level of capacitance. In such a case, leakage current is likely to occur, and thus, the implementation of the aforementioned dielectric structure may become limited in actual practice.